1. Field of the Invention
The invention, in general, relates to an amplifier and, more particularly, to an amplifier for use in integrated circuits and for digitally balancing the input offset voltage and amplification parameters with high precision at low technological complexity and on a small chip surface. Such amplifiers make possible precise digital adjustments of parameters, such as, for instance, amplifiers with zero-point correction. As well as to voltage amplifiers such as operational amplifiers for instance, the invention relates to amplifiers whose output parameter is a current, as, for instance, in operational transconductance amplifiers. In the case of the latter, transconductance will be the amplification to be adjusted.
2. The State of the Art
In the fabrication of integrated amplifiers, the balancing of parameters constitutes a significant problem. Balancing may take place during manufacture, for instance by the trimming of resistors with a laser, or by self-adjustment, using a built-in additional compensation circuit. As a rule, the latter provides a more economical solution in which the self-adjusting amplifier includes a compensating analog amplifier which, in addition to the conventional inputs for the signal to be amplified, is provided with a further analog input for compensating an adjustable parameter. Furthermore, the self-adjusting amplifier includes a compensation circuit for providing an adjustment value for the additional analog input. The adjustment value is determined during a compensation phase and is stored for the operational phase of the amplifier. Frequently, the purpose of the adjustment is to minimize the input offset voltage of the amplifier. This can be accomplished in various ways. In this regard, an overview is offered by R. Razavi in “Principles of Data Conversion System Design”, IEEE Press, 1995, chapter 8, “Precision Techniques”, pp. 198–231. As disclosed, for instance, by U.S. Pat. No. 6,242,974, the approaches chiefly involve volatile storage of the compensation value, usually as a charge of an integrated capacitance, for instance in conventional auto-zero amplifiers. Their advantage resides in small required chip surfaces; but their disadvantage is that, because of the small time constant of the discharge of the integrated capacitance, the adjustment must be repeated at short intervals, for instance at repetition rates in the kilohertz range. This generates an interference signal determined by the adjustment repetition rate. Hence, such amplifiers have a very restricted range of applications.
As regards applications or uses, a more advantageous solution is offered by non-volatile storage systems of a one-time adjustment, e.g. while energizing, of production-based errors without any subsequent interruptions of the operational phase. In the case of adjustments of greater precision, the adjustments may advantageously be repeated at longer intervals, for instance, every ten seconds, in order to compensate for changed parameters. Volatile storage in an integrated capacitance cannot provide such long operational phases. Known solutions involving non-volatile storage either require additional technological steps and a relatively long compensation phase by storing the compensation value in a “floating gate” (vide, for instance, M. Lanzoni, G. Tondi, P. Galbiati, and B. Ricco in “Automatic and Continuous Offset Compensation of MOS Operational Amplifiers Using Floating-Gate Transistors”, IEEE J. Solid-State Circuits, Vol. 33, pp. 287–290, February 19988), or they store a digitized adjustment value and use a digital-to-analog-converter to generate the necessary analog adjustment value (see, for instance, H. van der Plueg, G. Hoogzaad, H. A. H. Termeer, M. Vertregt, and R. I. J. Roovers in “A 2.5-V 12-b 54 M sample/s 0.25 μm CMOS ADC in 1-mm2 With Mixed-Signal Chopping and Calibration”. IEEE J. Solid-State Circuits, Vol. 36, pp. 1959–18677, December 2001).
Having regard to this latter approach in respect of which FIG. 1 depicts an exemplary digitally adjustable amplifier 100, the digital-to-analog-converter 130 must be of the requisite precision to be able to generate a sufficiently accurate value for adjusting the adjustable analog amplifier 110. The value may be controlled, for instance, in a digital control loop which includes a microprocessor 120 and a comparator 140. A control input 105 presets the instance of the adjustment. A handshake output 101 issues a signal indicative of the termination of the compensation phase. During the compensation phase, an input switch 150 switches the analog amplifier 110 such that the comparator 140 contains data relating to the adjustable parameter which is evaluated in the digital control loop for setting the analog amplifier 110. Elevated levels of precision in respect of the adjustment would require a complex digital-to-analog-converter provided, for this purpose, with self-adjusting elements and circuits. Such an arrangement would necessitate a much larger chip surface than the chip surface of the analog amplifier 110 itself and result in a considerable cost increase.
Thus, due to errors resulting from frequently repeated adjustments, the known solutions for adjusting parameters of integrated amplifiers either significantly restrict the range of application of such amplifiers, or they necessitate technological complexity or chip sizes which make the amplifier much more expensive. For that reason, most integrated amplifiers are manufactured without compensation circuits and suffer from significant errors, particularly in respect of the input offset voltage. In order to keep these errors within limits, further processes are necessary, such as assembling the input transistors in a symmetrical arrangement from a plurality of individual transistors. This requires chip surfaces of increased size and changes the behavior of the amplifiers, for instance, by increasing their input capacitance. Moreover, requirements of high precision can only seldom be satisfied.